Memory system having two clock pulse frequencies

ABSTRACT

A series connected dual memory system in which the clocking frequency of one memory is independent of the clocking frequency of the other memory. This system is designed to store and shift defective article information generated by an article inspection machine. The machine removes articles from a continually moving conveyor, indexes the articles one at a time through a series of inspection stations, generates a defect signal if an article fails to pass any one of the inspections, and returns all articles to the conveyor. A first memory stores defective article information. This information is shifted in the memory in synchronism with the index of the article through the inspection machine by a clock pulse at a frequency proportional to the index speed. Any defective article information is transferred into a second memory as the article to which the information pertains is replaced on the conveyor. As the article is moved away from the inspection machine, the information is shifted in the second memory in synchronism with the speed of the article by a clock pulse at a frequency proportional to the speed of the conveyor. When the information in the second memory reaches a rejection station downstream of the inspection machine, the rejection station is activated to remove the article from the conveyor.

United States Patent [1 1 Damm [ Sept. 11, 1973 MEMORY SYSTEM HAVING TWOCLOCK PULSE FREQUENCIES [75] Inventor: David A. Damm, Toledo, Ohio [73]Assignee: Owens-illinois, Inc., Toledo, Ohio 22 Filed: June '19, 1972[21] Appl. No.: 263,966

Primary Examiner-Richard A. Schacher Assistant ExaminerGene A. ChurchAttorney-Steve M. McLary et a1.

[57] ABSTRACT A series connected dual memory system in which theclocking frequency of one memory is independent of the clockingfrequency of the other memory. This system is designed to store andshift defective article information generated by an article inspectionmachine. The machine removes articles from a continually movingconveyor, indexes the articles one at a time through a series ofinspection stations, generates a defect signal if an article fails topass any one of the inspections, and returns'all articles to theconveyor. A first memory stores defective article information. Thisinformation is shifted in the memory in synchronism with the index ofthe article through the inspection machine by a clock pulse at afrequency proportional to the index speed. Any defective articleinformation is transferred into a second memory as the article to whichthe information pertains is replaced on the conveyor. As the article ismoved away from the inspection machine, the information is shifted inthe second memory in synchronism with the speed of the article by aclock pulse at a frequency proportional to the speed of the conveyor.When the information in the second memory reaches a rejection stationdownstream of the inspection machine, the rejection station is activatedto remove the article from the conveyor.

21 Claims, 44 Drawing Figures 58 57c 57d59c59l 59 Lfig 64 r 46 some llACHINE e CONVEYOR oenzcr' MEM RY' MEMORY LOGIC AND oE Ec-noN i 4.1'SQJQLSGg J 4% 424 50150: 45 m Patented Sept. 11, 1973 8 Sheets-Sheet 2w QE Pm: mm; mm 5 a m m 0 1 0 Q a U m G mm mm 3: Q2 M 0a om m w m n 1 Ql1 0 u U m U am 3 dz 2 @9 02 so. 0 Q Q m M 0x0 mama m i ll U L U M m 0 w0 cm cm a: :3 3m

Patented Sept. 11, 1973 8 Sheets-Sheet 5 l2 e LL 0 We FIG. If

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Patented Sept. 11, 1973 3,757,940

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MEMORY SYSTEM HAVING TWO CLOCK PULSE FREQUENCIES BACKGROUND OF THEINVENTION This invention relates to a memory for an article inspectionmachine. More particularly, this invention relates to a memory for anarticle inspection machine which removes articles from a conveyor,indexes the articles through a plurality of inspection stations,generates a signal if an article is defective, and returns all articlesto the conveyor. Most specifically, this invention relates to a memorysystem for inspection machines of the type described wherein two seriesconnected memories have information shifted in them at two independentclock pulse frequencies to allow rejection of defective articles at apoint downstream of the inspection machine.

One difficulty with any article inspection machine is the necessity ofproviding a memory. Generally in such machines, a plurality ofinspections are made at different locations. However, a defectivearticle cannot be rejected at the station which detects a flaw, since itis generally within the confines of the machine. Thus, a memory isprovided to remember a defective article and cause it to be rejectedwhen it is free of the inspection stations. Mechanical pin typeormagnetic belt memories have been used with some success. However, thesememories all require a rapid rejection after the end of inspection. Thisis true since the position of the article information within the memoryis a function of the rate of progress through the inspection machine.Thus, rejection must occur before the speed of index or travel of thearticle changes from that imparted by the inspection machine. Otherwise,the-correlation of the memory information with thearticle would be lost.Many systems of this type have been described in the prior art and areillustrated by US. Pats. Nos. 3,565,249; 3,263,810; 3,259,240; and3,581,889.1-Iowever, these systems were not capable of rememberingarticle defect information and rejecting a defective article after ithad deviated from its speed at the time of inspection. It is oftendesirable to remove the rejection area from the immediate proximity ofthe inspection machine. This function could not be done by the priorart. I have devised a memory system which transfers information, at thepoint of coincidence, from a first memory being clocked at a rateproportional to the inspection machine speedto a second memory systembeing clocked at a rate proportional to speed of a removal system forinspected articles. This allows remembering" information about anarticle to achieve rejection of a defective article from the removalsystem SUMMARY OF THE INVENTION My invention is an apparatus forinspecting and segregating articles which comprises the followingelements: conveyor means for moving articles in a single file; anarticle inspection machine located adjacent the conveyor means forreceiving articles one at a time from the conveyor means, seriallyindexing the articles through a plurality of inspection stations, andreleasing inspected articles to the conveyor means; an article defectlogic and detection means connected to the plurality of inspectionstations for generating one or more signals if an article is defectivein one or more aspects; a rejection means adjacent the conveyor meansdownstream of the inspection machine for removing deflective articlesfrom the conveyor means; first clock means for generating a series ofmachine clock pulses in synchronism with the index cycle of theinspection machine; first memory means connected to the article defectlogic and detection means and to the first clock means for storingdefective article information generated by the article defect logic anddetection means and for shifting the stored information in response tothe machine clock pulses of the first clock means in synchronism withthe index of the article from inspection station to inspection station;second clock means for generating a series of conveyor clock pulses insynchronism with the speed of travel of the conveyor means, thefrequency of the machine clock pulses and the conveyor clock pulsesbeing independent of one another; and second memory means connected tothe second clock means, the first memory means, and the rejection meansfor receiving defective article information from the first memory meansas the article is released to the conveyor means, for shifting theinformation in response to the conveyor clock pulses in synchronism withthe movement of the article along the conveyor means, and for actuatingthe rejection means as the article reaches the rejection means tothereby reject a defective article.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of anembodiment of the present invention showing the interrelation of theinspection machine, the article conveyor, the memory system, and therejection station;

FIG. 2 is a side, elevational view of the conveyor sig nal generator;

FIG. 3 is a side view of the code wheel of the'conveyor signal generatorof FIG. 2, removed from the apparatus shown in FIG. 2;

FIG. 4 is a schematic circuit diagram of the machine memory of FIG. 1;

FIG. 5 'is a schematic circuit diagram of the conveyor memory of FIG. 1;

FIGS. 6-2l'illustrate, in a schematic form, the progress of a defectivearticle along the article conveyor from the inspection machine to arejection means;

FIGS. 6A-21A illustrate, in a schematic form, the status of thedefective article information in the conveyor memory at each position ofthe article as shown I in FIGS. 6-21.

FIG. 22 is a schematic circuit diagram of the conveyor clock generator;

FIG. 23 is a schematic circuit diagram of the machine clock generator;FIG. 24 is a schematic circuit diagram of a typical reject signalconditioning unit; I

FIG. 25 is a schematic circuit diagram of another ical reject signalconditioning unit;

FIG. 26 is a schematic circuit diagram of a typical clock delay circuit;

FIG. 27 is a graph showing a series of wave forms to illustrate thegeneration of the machine memory clock pulse; and

FIG. 28 is a graph showing the machine memory clock pulse wave form, theconveyor memory clock pulse wave form, and the gauging pulse wave formon a common time base to illustrate the time relationship to these threewave forms.

DETAILED DESCRIPTION OF THE DRAWINGS FIG. 1 shows the mechanical andelectronic apparatus of the present invention in a schematic form. Thepresent invention is designed specifically to operate with a bottomgauging apparatus such as that described in U.S. Pat. No. 3,313,409, theteachings of which are hereby incorporated by reference. It is believedthat the teachings of the cited patent are sufficient to allow oneskilled in the art to utilize the present invention when described in aschematic form. The gauging apparatus or article inspection machine isgenerally designated by the numeral 9. A rotatable disk having pocketscut therein for receiving glass containers 12 to be inspected ispositioned over a constantly moving conveyor 14. In some cases, theconveyor 14 is actually divided into two independent segments. Thus, inthe broadest sense, the conveyor 14 is a conveyor means for deliveringand removing articles from the gauging apparatus 9. The conveyor 14presents containers 12 one at a time to the pocket of the rotatable disk10 designated as 1. As taught in U.S. Pat. No. 3,313,409, the container12 positioned in pocket number 1 is sequentially rotated to positionsnoted as 2, 3, 4, 5, 6 and 7. Inspection of the container is carried outat positions 2, 3, 4, 5 and 6 by apparatus which is not shown, but whichis well known to those skilled in the art. Position number 7, as notedin FIG. 1, is a position in which a container is held prior to itsrelease to the conveyor 14. If the container 12 has been passed by theinspection devices, the container is released and allowed to proceeddown the conveyor 14. In the prior art, if the container 12 were foundto be defective in some manner, it would then be held in position androtated to the position noted as 8 in FIG. 1, at which position it wouldbe rejected. The container 12 is held in position in position number 7by a tip 16 attached to the extending rod 18 of an air motor 20. The airmotor 20 is cycled in a manner to be described later. The air motor 20may be supported from the framework of the conveyor 14 by a supportbracket 21. It will be noted that the conveyor 14 has substantiallycontinuous inlet guide rails 24, which aid in guiding the container 12into the pocket noted as 1. There are, in addition, outlet guide rails26, which guide the container 12 after passage through the inspectionapparatus 9. It will be noted that at a position downstream from thepoint at which the container 12 is released to the conveyor 14 tocontinue its travel, the outlet guide rail 26 is interrupted on one sideby a space designated as 27. The space 27 is provided to allow rejectionof defective containers in a manner to be herein described; In addition,the opposite side of the conveyor 14 contains a moveable section of theguide rails 26 designated as 28. The moveable section 28 is shown in itsclosed position, with the open position shown in phantom lines. Themoveable section 28 is pivotally mounted on a conventional crankmechanism which is operated by the movement of the operating rod 30 ofan air motor 32. Containers 12, which are rejected through the gap 27 inthe outlet guide rails 26 fall onto a rejection conveyor 34, which iscommonly located somewhat below the plane of the conveyor 14, and areconveyed away for disposal.

It may be seen from-the block diagram of FIG. 1, that the memory systemof the present invention comprises three major components: a bottledefect logic and detection system 36, a machine memory 38 and a conveyormemory 40. The bottle defect logic and detection unit 36 is of the typewell known in the art and may be of the type such as that shown in U.S.Pat. No. 3,313,409. Signals from the detection equipment mounted abovethe rotatable disk 10 are fed into the bottle defect logic and detectionunit 36 through five input lines 42a, 42b, 42c, 42d and 42e. Aspreviously noted, the containers 12 are sequentially transferred frompositions 1 through 7 by the rotation of the rotatable disk 10. Toensure that the gauging of the container 12 is performed only when thecontainer 12 is in the proper position and the index cycle has ended, agauging switch 41 is provided. This switch may be'of the type such asthe switch 191 shown in U.S. Pat. No. 3,273,710, the teachings of whichare herein incorporated by reference. The purpose of the gauging switchis to provide a signal to the bottle defect logic and detection unit 36to accept a signal which enters the unit 36 through any one of thedefect signal lines 42 a through e. In FIG. 1, an output line 44 isshown as transmitting the bottle gauging pulse. The bottle gauging pulseis transmitted from the output line 44 through suitable electric wiringmeans 45 and 46 to the bottle defect logic and detection unit 36. Inaddition, the gauging pulse is transmitted through a wire 43 to a delayunit 47. The delay unit 46 controls the cycling of a solenoid valve 48.The solenoid valve 48 is connected to a source of air under pressure 50by a pipeline 51. The outlet of the solenoid valve 48 is connected tothe air motor 20 by a pipeline 52. The delay unit 47 accepts the gaugingpulse from the gauging switch 43 and performs a delay function to causethe air motor 20 to function as follows: just prior to the end of thegauging period, the delay unit 47 transmits a signal to the solenoidvalve 48 to admit air to the air motor 20. This causes the rod 18 toextend. The rod 18 remains extended during the transfer cycle to retaina container 12 which moves into position 7 on the rotatable disk 10.Then, the signal from the delay unit 47 ceases, the air to the air motor20 is stopped, and the rod 18 retracts. This allows the container 12 inposition 7 to move away on the conveyor 14 before the next transfercycle, thus leaving position 7 empty to accept the next container 12.The gauging pulse is also used as a clock pulse for the machine memory38. The gauging pulse is fed into a machine clock generator 54 by wiringmeans 53 connected to the electrical wiring means 45. Finally, thewiring means 53 is connected to an electrical wiring means 39 connectedto the conveyor memory 40. The output from the machine clock generator54 is fed into the machine memory 38 through suitable wiring 55. Thepurpose of the machine clock generator 54 is to provide a clock pulseinput through the wiring 55 to the machine memory 38 to allow bottlepresent and defective bottle information to be indexed as the container12 to which itpertains is indexed by the rotatable disk 10. There arefive output channels from the bottle defect and logic detection unit,56a, b, c, d and e. The defective bottle information carried by theoutput lines 56a through e is fed into the memory 38 and is indexed asthe container 12 to which the information pertains is indexed by therotatable disk 10. In addition, the defective bottle information is alsotransmitted to the machine memory 38, via a selector switch 58 throughlines 59a, b, c, d and e, which are selectively interposable between theinformation carried by the wiring 56a through e and the machine memory38. The selector switch 58 serves a .bottle save function which will beexplained in detail later. The final input to the machine memory 38 is abottle presence signal furnished through an electrical wire 60 connectedto a bottle presence switch 61. The bottle presence switch 61 isconveniently mounted on an arcuate guide rail 62 which surrounds therotatable disk and helps hold the containers 12 in their properposition. The bottom presence switch 61 is mounted adjacent to theposition noted as number 1 in FIG. I such that when a container 12 isindexed from the loading position or the number 1 position to the firstinspection position or the number 2 position, a signal is generated bythe bottle presence switch 61 and transmitted to the machine memory 38via the electrical wire 60'. The purpose of this function is to detectif a bottle 12 is in position at the gauging station and to ensure thata false rejection signal is not generated by the gauging apparatus 9 dueto the absence of a bottle at any one of the inspection stations.Finally the output of the machine memory 38 is fed into the conveyormemory 40. If any one of the inspection stations 2 through 6 determinesthat a container 12 is in some way defective, a rejection signal will betransmitted from the machine memory 38 to the conveyor memory 40 throughan electrical connection 64. The machine memory 38 has an additionaloutput to the conveyor memory 40 which is selective in nature and may beenergized by the use of the selector switch 58. This is a save signaland is transmitted to the conveyor memory 40 through an electrical wire66.The operational speeds of the rotatable disk 10 and the conveyor 14are not necessarily synchronized. Thus, it is necessary to generate aseparate clock input for the conveyor memory 40. This function isaccomplished by the conveyor signal generator 68 and conveyor clockpulse generator 65. The signal is transmitted from the conveyor signalgenerator 68 to the conveyor clock pulse generator 65 through electricalwiring 67, and the clock pulse is transmitted to the conveyor memory 40through suitable electric wiring 69. The details of the conveyor signalgenerator 68 are shown in FIGS. 2 and 3 and will be explained inconjunction with those figur'es. The output of the conveyor memory 40 isa signal to a solenoid valve 70 transmitted by suitable electric wiring71. The solenoid valve 70 is connected to the source of air underpressure 50 by a pipe 72. The output ofthe solenoid valve 70 isconnected to the air motor 32 by a pipe 74. When the solenoid valve 70receives a rejection signal through the wire 71, it opens and allows airto flow from the source of air under pressure 50 through the pipe 72,through the pipe 74, and into the air motor 32. This operates the rod ofthe air motor 30 and causes the moveable section 28 to function, therebyrejecting a container 12 in one of two selectable modes. As waspreviously noted, the moveable section 28 may move outward in such afashion that a container 12 is pushed through the space 27 and onto therejection conveyor 34 for removal. In addition, the machine memory 38,as will be explained later in detail, contains a function controlled bythe selector switch 58 which will allow a selected container 12 which isdefective to be saved for further examination. In such an event, themoveable section 28 is extended slightly in advance of the arrival ofthe container 12 at the rejection position, and the container 12 isguided off of the conveyor 14 and into a holding bin 76' for furtherexam: ination.

Turning now to FIG. 2, the conveyor signal generator 68 is shown in anend view for a further understanding of its functioning. An opaque codewheel 78 is rotatably mounted on a shaft 80 which is secured between thelegs of a substantially U-shaped housing 82 mounted above the conveyor14. The code wheel 78 is positioned above the conveyor 14 in such amanner that the movement of the conveyor 14 causes the code wheel 78 torotate at a speed corresponding to the lineal speed of the conveyor 14.As seen in FIG. 3, the code wheel 78 has four openings 83, 84, 85 and 86drilled completely through it, spaced at about intervals about itsperiphery. Also carried within the legs of the U-shaped housing 82 are aphotoelectric sensor 88 and a light source 90. The photoelectric sensor88 and the light source 90 are positioned substantially in alignmentwith one another such that if the code wheel 78 were not interposedbetween the photoelectric sensor 88 and the light source 90, thephotoelectric sensor 88 would be continually illuminated. However, thecode wheel 78 is interposed between these two elements, and, as itrotates, the photoelectric sensor 88 may receive light from the lightsource 90 only when one of the holes 83 through 86 pass in front of thelight source 90. It is this passage of the holes 83 through 86 in frontof the'light source 90 which generates the conveyor signals which areconverted into the clock pulsesby the-conveyor clock pulse generator 65.That is, each time the light source 90 is allowed to shine through oneof the four holes 83 to 86, the photoelectric sensor 88 produces asignal. As will be explained later in detail, the clock pulses are usedto operate the conveyor memory 40 in such a manner that the position ofa container 12 on the conveyor 14 is accurately represented after itsrelease from the exit position 7.

. A circuit diagram for the machine memory 38 is shown in FIG. 4. Itwill first be noted that there are three independent, parallel memoryunits contained within the machine memory 38. Each of the three parallelmemory units is made up of six identical flipflop units connected inseries. The flip-flops may be a model MC 664 manufactured by theMotorola Corporation. Each of the flip-flop units have seven terminalsavailable for connection. The input terminals are labeled S for set andR for reset. The output terminals are labeled 0" and Q. In addition,there are terminals labeled SD for direct set and RD for direct reset.

A signal into the SD" or the RD" terminal may change the operationalstate of the flip-flop regardless of the input signals. The finalconnection available for the flip-flops is the terminal labeled C whichis the clock input terminal. A pulse into the clock input terminal willcause the flip-flop to assume whatever state is indicated at the 8" andR" terminals.

The uppermost memory unit or defective bottle memory is composed of sixidentical flip-flops, 92, 93, 94, 95, 96 and 97 connected in series. Thefirst flip-flop in the series 92 has a voltage source 98 connected tothe "S" terminal. The "R" terminal of the first flip-flop 92 isgrounded. This configuration ensures that the first flip-flop 92 isbiased in the onf condition. The SD" terminals of all of the flip-flops92 through 97 are connected in common to a voltage source 99 whichensures that no signal can be transmitted to the SD terminal, therebyinadvertently changing the state of any of the flip-flops 92 through 97.In addition, it will be noted that the same voltage source 99 isconnected to the RD terminal of the final flip-flop 97 in the firstmemory series. Thisis required because the final flipflop 97 receives nobad bottle information but is simply used as an output to the conveyormemory 40. Thus, it is necessary to ensure that a signal cannot bereceived on either the SD or the RD" terminals of the flipflop 97 andensure that the memory information therein is retained. The RD terminalsof the flip-flops 92 through 96 are connected to identical reject signalconditioning units 100 through 104 (see FIG. 24). The signalconditioning units 100 through 104 have two independent inputs. One ofthe inputs is a bad bottle signal as transmitted by the electricalwiring means 56a through 56:2. The other input is a bottle presencesignal, the generation of which will be discussed in conjunction withthe second parallel memory unit.

The clock signal is transmitted from the wiring 55 into the flip-flops92 through 97. it will be noted that the first flip-flop which receivesthe clock pulse is the flip-flop 97 This, of course, is conventionalpractice in shift register type memory systems, since the flow ofinformation is from right to left as viewed in FIG. 4. The clock signalis delayed by five identical clock delay circuits 106 (see P16. 26). Thepurpose of the clock delay circuits 106 is to ensure that the clockpulse is delayed between the flip-flops 96 through 92 to prevent earlyarrival of the clock pulse to a preceding shift register and theconsequential destruction of the information contained therein beforethe information can be read out into the subsequent flip-flop. That is,the occurrence of a pulse at the C or clock terminal of any one of theflip-flops 92 through 97 is in effect a signal to the flip-flop to wipeout whatever information it contains at that time and assume that stateseen by its S and R" terminals. Since all of the flip-flops 92 through97 are connected in series with the Q terminal of one flip-flopconnected to the 8" terminal of the next flipflop and the Q terminalconnected to the R" terminal, this then means that the occurrence of apulse at the C terminal will set the flip-flop in whatever state the Qand Q terminals of the preceding flip-flop had assumed. This then is thememory function and allows information placed in one of the flip-flopsto be moved sequentially from right to left as the clocking pulsesoccur.

The flip-flop 92 is electrically connected to the reject signalconditioning unit 100 such that an output pulse from the reject signalconditioning unit 100 will be en tered in the RD terminal of theflip-flop 92. A signal from the reject signal conditioning unit 100indicates that a defective bottle signal has been entered through theelectrical wiring 56a into the reject signal conditioning unit 100. Sucha signal will overcome the initial condition presented by the voltagesource 98 to the "5 terminal of the flip-flop 92 and set the flip-flop92 in a condition indicating that a bad bottle was detected at stationnumber 2 in the gauging apparatus 9. it should be noted at this pointthat the logic used throughout this system is essentially alogic whichindicates the presence of an information signal by the lack of voltage.That is, all of the logic is preplanned such that the occurrence of adefect signal from the gauging apparatus 9 will result in one of theshift registers 92 through 96 being cleared to a zero state. This then,in turn, means that when the clock pulse reaches the flip-flop 93, theflip-flop 93 will see a zero input from the flipflop 92 if the flip-flop92 possesses a defective bottle signal. Then, after the delay impartedby the clock delay circuit 106 interposed between the flip-flops 93 and92, the clock pulse will cause the flip-flop 92 to assume the one or onstate, due to the initial condition input voltage from the voltagesource 98. The zero or off" information then passed to the flip-flop 93will be, in turn, passed to the flip-flops 94, 95, 96 and 97 bysubsequent clock pulses. Thus, the information indicating a defectivebottle will finally be passed to the flipflop 97. I

The center parallel memory circuit is provided to retain information asto the presence or absence of a container 12 in the inspection apparatus9. It should be readily apparent that, again, six identical flip-flops108 through 113 are connected in series. The final flip-flop 113 isactually not needed, since all of the defect information has beenprocessed by this point and bottle presence information is no longerneeded. However, for ease of construction, the sixth flip-flop 113 isprovided. These flip-flops 108 through 113 are identical to theflip-flops previously described in conjunction with the defective bottlememory circuit. Again, the S terminal of the first flip-flop 108 isbiased in the on position with a voltage source 114. The R terminal ofthe flip-flop 108 isagain grounded. In addition, however; both the RDand the SD terminals of all of the flip-flops 108 through 113 areconnected to a voltage source 115 to present an initial conditionvoltage to these terminals such that stray signals cannot change thestate of the flip-flops 108 through 113 except through the RD terminalof flip-flop 108. The bottle presence flip-flops, 108 through 113receive their only informational input signal via the electrical wiringinto the RD terminal of the first flip-flop 108 from the bottle presenceswitch 61. An input dropping resistor 107 is connected to the RDterminal of the flipflop 108 to ensure that a signal from the switch 61is not transmitted to the other flip-flops 109-113. Thus, as a container12 moves from position 1 to position 2 on the rotatable disk 10, asignal is generated by the switch 61 and transmitted to the firstflip-flop 108 setting the condition of the flip-flop 108 to zero. Again,it should be noted that the initial condition input voltage source 114would normally retain the state of the flipflop 108 in the on or onestate. However, the RD terminal allows overriding the input source 114and will thus accept the signal from the bottle presence switch 61. itwill be noted in FIG. 4 that the output of the bottle presence switch 61is actually grounded, thus presenting a ground signal to the RD terminaland overcoming the initial condition voltage of the voltage source 1 l5and allowing the flip-flop 108 to assume the zero or off state. Then, aswas the case with the series of flip-flops 92 through 97, the bottlepresence information is transmitted in sequence from the flip-flops 108through 113 as the input clocking pulses occur. It will be noted thatthe clock terminals or "C" terminals of the flip-flops 108 through 113are directly connected to the outputs of the clock delay circuits 106used for clocking the flip-flops 92 through 97. Thus, the bottlepresence information proceeds at the same clock rate as does thedefective bottle information in the first memory circuit. The bottlepresence signal is transmittedfrom the "Q" output terminals of theflip-flops 108 through 113 into the reject signal conditioning units 101through 104 through suitable electrical wiring means 117 through 121. Itis not necessary to continue the transmission of the bottle presencesignal into the conveyor memory since bottle presence is a prerequisitefor having reject information in the defective bottle memory chain.

The final of the three parallel memory systems which make up the machinememory 38 is a series connected six-stage flip-flop system which is usedto retain information about specific containers 12 that are to be savedfor further analysis. That is, given the first two memory systems madeupof the flip-flops 92 through 97 and the flip-flops 108 through 113,defective con tainers 12 would simply be rejected when they reached arejection point. However, under some circumstances, it may be desirableto save specific containers'12 which are rejected by a particular one ormore of the five rejection stations carried by the inspection apparatus9. Thus, the selector switch 58 is provided to allow a signal to beplacedinto one of six series connected flipflops 124 through 129, whichmake up the bottle save memory. Again, the flip-flops 124 through 129are identical to the flip-flops 108 through 113 and 92 through 97. Avoltage source 130 is connected to the S terminal of the first flip-flop124 and is used to create an initial condition in the flip-flop 124 ofan on" or one state. The R terminal of the first flip-flop 124 is againgrounded. The SD terminals of all of the flipflops 124 through 129 areconnected to a voltage source 132 which prevents the entry of any signalinto these particular terminals. In addition, the source 132 is alsoconnected to the RD" terminal of the final flip flop 129, since noinformational signal will be received by this particular unit. Again,the flip-flops 124 through 129 are connected in common with the clockinput line 55 and the clock delay circuits 106 to ensure that theclocking pulses for all three of the units of flip-flops 92 through97,108 through 113, and 124 through 129 process information from stageto stage at the same rate. The input to the RD terminal of theflip-flops 124 through 128 is fromreject signal conditioning units 134,135, 136, 137 and 138. The reject signal conditioning units 134 through138 are identical in electrical configuration to the reject signalconditioning units 100 through 104 (see FIG. 25). One of the inputs tothe reject signal conditioning units 134 through 138 is the signal fromthe Q output terminals of the flip-flops 108 through 112 which containthe bottle presence information. Defective bottle information istransmitted to the selector switch 58 from the defective bottle signallines 56a through e by input wiring 57a through e. The output of theselector switch 58 is connected to the reject signal conditioning units134 through 138 through output wiring 59a, 59b, 59c, 59d and 5942. Theselector switch 58 is of a sliding wire type which allows any one of theinput lines 57a through e to be connected to its respective output line590 through e. However, it should be realized that more than oneselector switch 58 could be used to allow saving containers 12 rejectedfrom more than one inspection station. In the configuration shown inFIG. 4, the defective bottle information carried by the input wiring 570is connected to its respective output wire 59c. 59c, in turn, isconnected to the signal conditioning unit 136, which is connected to theRD" terminal of the flipflop 126. This, then, means that should adefective bottle signal be transmitted from the station indicated as 4on the rotatable disk 10, the signal will be transmitted through theinput wire 570 to the output wire 59c and,

in turn, to the reject signal conditioning unit 136. This signal then,assuming that a bottle presence signal is received from the flip-flop110, will be transmitted to the RD terminal of the flip-flop 126. Thiswill reset the condition of the flip-flop 126 and cause the signal to bepropagated to the flip-flops 127, 128 and 129 in turn as the properclocking signal is received. This information is then fed to theconveyor memory 40 through the output line 66.

At this point, it is necessary to understand that the machine memory 38and the conveyor memory 40 do not necessarily operate at the sameclocking rate. That is, the speed of operation of the gaugingapparatus 9does not have a direct correlation with the speed of the conveyor 14.This means that the two memory systems 38 and 40 must have independentclocking input pulses to retain the position of a defective container 12for proper rejection. Thus, a transfer must be made of the informationcontained withinthe machine memory 38 to the conveyor memory 40 at apoint where the two systems are coincident. The only position at whichthis occurs in the entire cycle is when a container 12 is in the outputposition designated as 7 of the rotatable disk 10. At this point, theinformation contained in the flipflop 97 and any information infiip-flop 129 is transferred to the conveyor memory 40.

FIG. 5 illustrates the circuit of the conveyor memory 40. The circuititself will be explained first and then the functioning of the circuitand the memory transfer function will be explained later in detail. Theconveyor memory 40 is shown as a l2-stage flip-flop type shift register,having 12 identical flip-flops through .151 connected in series. Theflip-flops 140 through 151 are identical to the flip-flops previouslydescribed and used in the machine memory 38. It should be understoodthat the use of 12 flip-flops 140 through 151 for the conveyor memory 40is a matter of convenience. It would be possible to use fewer than 12flip-flops or more than 12 flip-flops, depending on the downstreamposition at which it was desired to rejector save a defective container12. It will first be noted that the S terminal of the first'flip-flop140 is given an initial coridition by the use of an input voltage source152. Again, the R" terminal of the flip-flop 140 is grounded, thusplacing the flip-flop 140 in the on or one state. All of the SD and RDterminals of the flip-flops 140 through 151 are connected to a voltagesource 153, which again is used to prevent accidental switching of thestates of any of the flip-flops. The defective bottle informationtransmitted by the output line 64 first goes through an inverting NANDgate 200 -in the conveyor memory 40. The output of the NAND gate 200 iscarried by wiring 202 to a summing NAND gate 204. The other input to theNAND gate 204 is a wire 206 which carries the gauging signal'which hasbeen inverted by an inverting NAND gate 208. A delay capacitor 201 isinterposed in the line 202 between the NAND gate 200 and the NAND gate204. The delay capacitor 201 delays the arrival of the defective bottleinformation at the summing NAND gate 204 slightly to allow the gaugingsignal (transmitted through the line 39) to become stable beforetransferring information into the conveyor memory 40. When both inputsinto the summing NAND gate 204 are l or high, the output of the NANDgate 204 will be zero or low. This signal is transmitted via wiring 210to the RD" terminal of the flipflop 140. An input droppingresistor 212ensures that any signal from the line 210 will not be propagated to theother flip-flops in the conveyor memory 140. The information that abottle 12 is to be saved is entered through the line 66, and is treatedin an identical manner using an inverting NAND gate 214, an output 216from the gate 214, a delay capacitor 215, a summing NAND gate 218, anoutput line 220 from the gate 218 connected to the RD terminal of theflip-flop 142, and an input dropping resistor 222. It will be noted thatthe save information is not transmitted to the second flip-flop in theseries connection, 141, but rather is transmitted to the third flip-flop142. The purpose of this wiring arrangement will becomeobvious when thetransfer of memory function is described later. The conveyor clock inputpulse is transmitted via the line 69 as previously described. This pulseis first transmitted to the last flip-flop in the series connection 151.Again, a plurality of clock delay circuits 106 are interposed betweenthe various flip-flops to ensure that the clock signal does not arriveat any one of the flip-flops 140 through 151 until the flip-flop hasbeen able to read the information contained within the precedingflip-flop. Finally, the output of the last flip-flop 151 is transmittedvia the output signal line 71 to the solenoid valve 70 which controlsthe functioning of the reject and save mechanism. I

The transfer of information from the machine memory 38 to the conveyormemory 40 and the save the reject functions of the conveyor memory 40are shown in schematic form in FIGS. 6 through 21 and FIGS. 6A-21A. Theconveyor memory 40 flip-flops 140 through 151 are simply shown as blocksin FIGS. 6A through 21A. An X in one of the blocks indicates thatinformation is present in that particular flip-flop 140 through 151. Itwill be understood that the presence of the mark in the blockrepresenting the flip-flop is generally taken to indicate the flip-flopas being in the on state. However, as previously explained, the logic ofthis particular system operates in such a mode that the presence ofinformation is indicated by the flipflop being in the "off state.However, those skilled in the art will readily recognize that the choiceof this particular logic configuration is simply a matter ofconvenience, and the entire system could be readily operated in such amode that the presence of information could be indicated by theflip-flop being in the on" state. It is believed that the understandingof the functioning of the memory transfer and the reject function willbe facilitated by representing the presence of information with an X inthe blocks representing the flip-flops 140 through 151. Beginning withFIGS. 6 and 6A, the configuration shown is that immediately after thecontainer 12 has been indexed to the final or output station 7 by therotatable disk 10. At this point, assume that the container 12 inposition 7 has exhibited some defeet and it is desired to save thisparticular container 12. Thus, the machine memory 38 received a clockpulse during the transfer of the container 12 from position 6 toposition 7 (see FIG. 28). The receipt of the gauging pulse by the NANDgate 208 caused the flipflops 97 and 129 to read their information intothe flipflops 140 and 142 as shown in FIG. 6A. Thus, information ispresent in flip-flops 140 and 142. As indicated on the wave formdrawings (see FIG. 28), the conveyor clock pulses continue at a constantrate even during the inspection apparatus 9 gauging cycle when there areno clock pulses to the machine memory 38. Thus, FIGS.

7A and 8A show that clock pulses to the conveyor memory cause theinformation output from the flipflops 97 and 129 to be repeated intoconveyor flip-flops 140 and 142 during the gauging cycle. Therefore, asshown in FIG. 8A, a total of five flip-flops 140 through 144 are in theinformation indicating state at the end of the machine gauging cycle. InFIG. 9, the container 12 has begun to move down the conveyor 14. It isassumed that the next container placed in position 7 was not a defectivecontainer, and thus no defect information was carried by the flip-flop97 to be transferred to the flip-flop 140. At this point then, theconveyor memory 40 has left the influence of the machine memory 38 andno further information pulses will enter the conveyor memory 40.Therefore, as shown in FIG. 9A, the next conveyor clock pulse will movethe information down one step in the flip-flop shift register. This willleave the flip-flop 140 blank, and the flipflops 145 through 141 will becarrying information. It should now be apparent that the informationrelating to the container 12 is carried in a block of flip-flops, inthis case five in number. Therefore, .the positioning of the container12 on the conveyor 14 is not particularly critical at this stage. Thisis important, sincethe conveyor 14 will not always convey a container 12at identically reproducible positions. There may be some slip betweenthe conveyor 14 and a particular container 12 leading to some positionalvariation of containers 12 on the conveyor 14. By allowing the rejectfunction to take place over a time span, the positional variations ofthe container 12 on the conveyor 14 may be compensated for. FIGS. 10through 14 and FIGS. 10A through 14A illustrate the movement of theinformation relating to the container 12 through the various flip-flopsas the container 12 is conveyed toward the rejection point. It should berealized that during this time, the rotatable disk 10 is indexing,moving a new container 12' into the output position 7 and inspectingadditional containers. FIGS. 15 and 15A illustrate that, at the timethat a new container 12 is released to the conveyor 14, the defectivebottle information has reached the final stage in the conveyor memory40, namely the flip-flop 151, and has produced an output pulse on theoutput line 71 to the solenoid valve 70. It should be recognized that,depending on the speed of the gauging apparatus 9 and the number offlip-flops in the conveyor memory 40, it might be possible to have aplurality of containers 12 between the gauging apparatus 9 and themoveable section 28 on the conveyor 14. The pulse, in turn, opens themoveable section 28. As the container 12 continues to move forward, thetrain of pulses through the flipflop 151, moved by the clocking pulsesthrough the conveyor memory 40, hold the moveable section 28 open. Whenthe container 12 reaches the moveable section 28, it is deflected off ofthe conveyor 14 and into the holding bin 76. It will be noted, in FIG.6A, that the initial informational pulses were placed in the flip-flopsand 142. By placing the bottle save information in the flip-flop 142, alead time of at least two conveyor clock pulses was obtained. Thisallowed the moveable section 28 to open before the conveyor 12 reachedthe rejection position. Had the information to save not been placed inthe flip-flop 142, FIG. 6A would simply have shown an informational bitin the flip-flop 140. Thus, there would have been a train of only threepulses rather than the train of five pulses as shown. It may thus beappreciated that the moveable section 28 would not open until the timeshown in FIGS. 17 and 17A. In such a situation, the defective container12 would have been forcibly swept through the opening 27 in the guiderails 26 and onto the rejec tion conveyor 34 by the moveable section 28.

Continuing now, it may be seen that the moveable section 28 will remainopen in FIGS. l8, 13, 18A, and 19A, even though the defective container12 has already been diverted into the holding bin 76. In addition, thecontainer 12' released after the defective container 12 has beensteadily moved by the conveyor 14 toward the rejection point. However,before the second container 12' can reach the rejection point, as shownin FIGS. 20 and 20A, the train of informational pulses ends and themoveable section28 closes. Thus, it can easily be seen in FIGS. 21 and21A that the second con.- tainer 12 will pass by the rejection pointwithout being diverted from its path of travel.

The clock pulse for the machine memory 38 and the circuit for generatingthe clocking pulse may be seen with reference to FIGS. 23 and 27. FIG.27 is a series of wave forms showing the actual generation of theclocking pulse, which is designated as wave form F. It will be notedthat the voltage levels are designated in the logic manner as either 1or in FIG. 27. As previously discussed, the gauging switch 41 is in theon position during the actual gauging cycle as illustrated by wave formA in FIG. 27. The machine clock generator 54 shown in FIG. 23 has, asaninput, the wave form A from the gauging switch 41. A noise suppressioncapacitor 155 is connected in parallel with the gauging switch 41. Avoltage source 156 feeding through a resistor 157 serves as the powerinput for the gauging switch 41. As seen in FIG. 23, the wave form Aappears at the input to the machine clock generator 54. A first NANDgate 158 receives the gauging pulse A and inverts it to give a positivegoing pulse designated as wave form B. The wave form B is then connectedto a second inverting NAND gate 159 which will reinvert the wave form B.However, a delay capacitor 160 is interposed in the path of travel ofthe wave form B and must be discharged before the signal can bepropagated from the second inverting NAND gate 159 to a third invertingNAND gate 161. The delay capacitor 160, which is grounded, has aparticular discharging curve characteristic which causes the output ofthe second NAND gate 159 to assume the wave form shown as C in FIG. 27.The result of the delay characteristics is that the switching levelrequired to turn the NAND gate 161 on is not reached until a shortperiod of time after the wave form B has reached the second NAND gate159. This may be seen in FIG. 27 as wave form D. Specifically, note thatwave form D is displaced slightly to the right in FIG. 27 from the "ontime shown for wave form B. A fourth NAND gate 162 has as its input thewave form D a well as the wave form A. It is the fourth NAND gate 162which actually performs the final shaping function of the machine memoryclock pulse. It willbe recalled at this point that the wave form D hasbeen generated and is in the on" condition. When the gauging cycle hasended, the wave form A will again raise to the high" or one value. Thiswill immediately cause the wave form B to drop to the low" or "zero"value. However, the propagation of the wave form B from the NAND gate159 will be delayed by the delay capacitor 160. In this case, the timeat which the NAND gate 163 will be turned ofi will be delayed a shortperiod of time after the NAND gate 159 has been turned off. The netresult is that the total wave form D is slightly displaced to the rightof the wave form B. In addition, the wave form designated as E in FIG.27, which is generated by the NAND gate I62, may be generated onlyduring a very short period of time when both the wave form A and thewave form D are in their high or one condition. It will be recalledagain that the combination of the waveforms D and Ccause the wave form Dto slightly lag the turning on of the gauging switch 41. This means thata short period of time after the gauging cycle has ended and when thetransfer cycle has begun, the wave form A and the wave form D will bothbe in the high or one condition. The characteristics of a NAND gate, asis well known, are such that there will be a zero output only when bothinputs are one. Therefore, the very short pulse E is generated as theoutput of the NAND gate 162. A fifth NAND gate 164 is used to invert thewave form E to give the wave form F, which is actually the clockingpulse. The NAND gate 164 is necessary since the flipflops used in thelogic system require the falling edge of a positive going clock pulsefor operation and consequently the wave form E must be inverted to givethe wave form F, displaced in time from the end of the gauging cycle. Itshould now be realized that the clocking pulse F is generated only afterthe gauging cycle has been completed. This ensures that any defectivebottle information has been transmitted to the machine memory 38 beforethe clocking pulse F maybe received by the machine memory 38 to transfersuch information'to the next stage in the machine memory 38. In effect,the clocking pulse F is triggered by the rising edge of the end of thegauging cycle. v

Keeping in mind the foregoing description, the conveyor clock pulsegenerator 65 as shown in FIG. 22, it may be seen that the conveyor clockpulse generator 65 is essentially identical to the machine clockpulsegenerator 54. The operations performed on the incoming signals areidentical and the output pulse is identical in the sense that the outputclock pulse is a shaped, relatively narrow pulse for the clockingfunction. In the case of the conveyor clock pulse generator 65, theinput signal is through the line 67 connected to the conveyor signalgenerator 68. It is believed that the discussion of the machine clockpulse generator 54 is sufficient to allow a simple description of thecomponents of the conveyor clock pulse generator 65 without giving thedetails of the actual shaping of the clocking pulse. The signal from theconveyor signal generator 68 is first amplified with a signal amplifier166. Then, the signal passes through five identical NAND gates I68, 169,170, E71 and 1172. Additionally, a grounded delay capacitor 174 isplaced in'circuit between the NAND gates 169 and 1170. The NAND gate171, as was seen with respect to the NAND gate 162, has two inputs. Oneinput is the amplified conveyor signal and the other input is from theNAND gate 170. FIG. 28 illustrates a plurality of gauging pulses A,machine memory clock pulses F, and conveyor clock pulses which aredesignated as wave form G. The illustration of FIG. 28 is on a commontime base, so that the relationship between the occurrence of thegauging pulses A, the machine memory clock pulses F and the conveyormemory clock pulses G may be readily seen. It may now be appreciated, byreference to FIG. 28, that a number'of conveyor clock pulses G may occurduring the actual gauging period. However, only one machine memory clockpulse occurs for each unique gauge period. Thus, the previouslyexplained movement of information in the conveyor memory during theactual gauging period may now be appreciated.

FIGS. 24 and 25 illustrate two typical reject signal conditioning units100 and 134. The unit 100 may be considered typical of the units 100through 105, and the unit 134 may be considered typical of the units 134through 138. The unit 100 receives one input signal through the wire 56Aconnected to the bottle defect logic unit 38. An additional input isthrough the wire 117 connected to the Q terminal of one of the bottlepresence flip-flops 108. The signal transmitted on the line 117 is sentthrough an inverting NAND gate 176 which changes the zero level signalfrom the Q terminal to a one" level signal. The one level signal is thentransmitted into a NAND gate 178 where it is combined with the signalcarried by the wire 56A. The logic of the bottle inspection apparatus issuch that defective bottle information is in a one" condition. Thus, ifboth inputs into the NAND gate 178 are one, the output of the NAND gate178 will be zero. This zero" signal is then fed to the RD terminal ofthe flipflop 92 to indicate the presence of a defective container. Inthe reject signal conditioning unit 134, the bottle presence signal isagain introduced through the wiring 117. Once again, this signal isinverted by a NAND gate 180. In this configuratiom'any input into thesecond NAND gate 182 is through the wiring 59A. It will be recalled thatthe wire 59A is a part of the array 59A through 59E which is the outputof the selec tor switch 58. As with the reject signal conditioning unit100, the NAND gate 182 will give an output if both the signal out of theNAND gate 180 and the signal in the wire 59A are on or in the onecondition. In this case, the output of the reject signal conditioningunit 134 is fed to the RD terminal of the flip-flop 124 in the bottlesave memory.

Finally, FIG. 26 illustrates one of the plurality of clock delaycircuits 106. Each clock delay circuit is made up of two NAND gates 184and 185 connected in series. The input to the first NAND gate 184 is theclock wave pulse F, which is transmitted on the wire 55. The first NANDgate 184 inverts the clock wave form F and, if it were not for agrounded delay capacitor 186 interposed between the NAND gates 184 and185, the pulse would simply be reinverted by the NAND gate 185 to itsoriginal form. However, the delay capacitor 186 delays propagation ofthe clock pulse from the NAND gate 184 to the NAND gate 185 as waspreviously illustrated in FIGS. 27 and 23 with respect to the delaycapacitor 160. The net result is that the propagation of the machinememory clock pulse is delayed slightly between flip-flop stages to allowthe transfer of information from one stage to the next before the clockpulse clears that particular stage of the fllp-flop. The clock pulse,after the delay imparted by the delay capacitor 186, leaves the clockdelay circuit 106 in an identical form and pulse width as that in whichit entered the clock delay circuit 106, but its time interval has beenextended beyond that which would occur if the clock delay circuits 106were not interposed in the path of the machine memory clock 6 pulses.

What I claim is:

1. Apparatus for inspecting and segregating articles comprising, incombination:

conveyor means for moving said articles in single file;

an article inspection machine located adjacent said conveyor means forreceiving said articles one at a time therefrom, serially indexing saidarticles through a plurality of inspection stations, and releasinginspected articles to said conveyor means;

an article defect logic and detection means connected to said pluralityof inspection stations for generating one or more output signals if anarticle is defective in one or more aspects, said article defect logicand detection means having a plurality of output leads at least equal innumber to the number of said inspection stations;

a rejection means adjacent said conveyor means,

downstream of said inspection machine, for removing defective articlesfrom said conveyor means;

first clock means for generating a series of machine clock pulses insynchronism with the index cycle of said inspection machine;

first memory means connected to said article defect I logic anddetection'means and to said first clock means for storing defectivearticle information generated by said article defect logic and detectionmeans and for shifting said information in response to said machineclock pulses of said first clock means in synchronism with the index ofsaid article from inspection station to. inspection station;

second clock means for generating a series of conveyor clock pulses insynchronism with the speed of travel of said conveyor means, thefrequency of said machine clock pulses and said conveyor clock pulsesbeing independent of one another; and

second memory means connected to said second clock means, said firstmemory means and said rejection means for receiving defective articleinformation from said first memory means as said article is released tosaid conveyor means, for shifting said information in response to saidconveyor clock pulses in synchronism with the movement of said articlealong said conveyor means, and for actuating said rejection means assaid article reaches said rejection means to thereby reject a defectivearticle.

2. The apparatus of claim l, further including:

selector means connected to said article defect logic and detectionmeans for choosing one of said inspection stations to provide an outputfrom selector means when a defective article is present at saidinspection station; and

third memory means connected to said first clock means, said firstmemory means, said selector means and said second memory means forreceiving defective article information from said selector means, forshifting said information in response to said machine clock pulses ofsaid first clock means in synchronism with the index of said defectivearticle from inspection station to inspection station, and for insertingsaid information in said second memory means in a position leading theposition wherein the same information is inserted in said second memorymeans by said first memory means.

3. The apparatus of claim 2, wherein said first memory means comprises,in combination:

a first plurality of flip-flops connected in series to form a shiftregister, said plurality of flip-flops being at least equal in number tothe numberof inspection stations; 1

a second plurality of flip-flops connected in series to form a shiftregister, said second plurality of flipflops being at least equal innumber to the number of said first plurality of flip-flops;

means connected to said first and second plurality of flip-flops forsetting an initial condition in all of said first and second pluralityof flip-flops;

an article presence switch adjacent said article inspection machine,connected to the first one of said second plurality of flip-flops, forovercoming the initial condition of said first one of said secondplurality of flip-flops when an article is present for inspection;

a first plurality of independent signal conditioning means, each of saidfirst plurality of signal conditioning means having one inputrespectively connected to one of said plurality of output leads fromsaid article defect logic and detection means, for resetting said firstplurality of flip-flops; I

means for connecting the output of said first plurality of signalconditioning means respectively to an input of individual ones of saidfirst plurality of flipflops;and v 5 means for connecting the outputs ofsaid second pluond plurality of signal conditioning means comprises,

in combination:

a first NAND gate having its input side connected to one of said secondplurality of flip-flops; and

'a second NAND gate having one input connected to the output of saidfirst NAND gate and having a second input connected to said selectormeans, and having its output connected to one of said third plurality offlip-flops. 7. The apparatus of claim 2, wherein said first clock meansincludes means for generating a signal during 20 the gauging cycle, andsaid second memory means rality of flip-flops respectively to a secondinput of each of said firstplurality of signal conditioning means,whereby said first plurality of signalconditioning means will reset saidone of said first plurality of flip-flops only when a defective articleis detected and when said second plurality of flip-flops indicates thepresence of an-article at the inspection station where the defectivearticle is detected, 4. The apparatus of claim 3, wherein said thirdmemory means comprises, in combination:

a third plurality of flip-flops connected in series to form a shiftregister, said third plurality of flip-flops being at least equal innumber to the number of inspection stations;

means connected to said third plurality of flip-flops for setting aninitial condition in'all of said third plurality of flip-flops; I 1

a second plurality of independent 'signalconditioning means, each ofsaid second plurality of signal con ditioning meanshaving oneinputrespectively connected to one of the outputs of said selector means,forresetting said third'plurality of flip-flops; means'for connectingthe output of said second p'lurality of signal conditioning meansrespectively to an input of individual ones of said third plurality offlip-flops; and means for connecting the'outputs of saidsecond-plurality of flip-flops respectively 'to a second input of eachof said second plurality of signal conditioning means, whereby saidsecond plurality of signal conditioning means will reset said one ofsaid third plurality of flip-flops only when a defective article isdetected at the inspection station connected to one of said secondplurality of signal conditioning means through said selector means andwhen said second plurality of flip-flops indicates the presence of anarticleat the inspection station where the defective. article isdetected.

5. The apparatus of claim 3, wherein each of said first plurality ofsignal conditioning means comprises, in

combination:

comprises, in combination:

a plurality of flip-flops connected in series to form a shittregister; sT means connected tosaid plurality of flip-flops for setting an initialcondition in 'all of said-flip-flops; signal conditioningmeans-havingone-output connected to the first one of saidpluralityofflip-flops and a second'output corinectd to a subsequent one of saidflip-flops for resetting said'first one and said subsequent onefof saidflip-flops when a signal is presented by said first memory means andsaid third memory means and when said gauging signal is present or forresetting only said first one of said flip-flops when'a signal ispresented only by said first memory means and said, gauging signal ispresent; 1 means for connecting the output of said third memory means toa first input of said signal conditioning means; I means for connectingsaid gauging signal to a second A input of said signal conditioningmeans; and r H means for connecting the outputof said first memory meansto a third input of said signal conditionin means. I r v 8. Theapparatus of claim f! wherein said signal conditioning meanscomprises,'in combination; I

a first NAND "gate having its input connectedto said first input of saidsignal conditioning means;

a second NAND gate having its input connected to said second input ofsaid signal conditioning means; i

a third NAND gate having its input connected to said third input ofsaidsignal conditioning means;

a fourth NAND gate having one input connected to the output of saidfirst NAND gate and having a second input connected to the output ofsaid second NAND gate, and having its output connected to saidsubsequent one of said plurality of flip-flops;

a first delay capacitor connected in circuit between said first NANDgate and said fourth NAND gate for delaying the propagation of a signalfrom said first NAND gate to said fourth NAND gate;

a fifth NAND gate having one input connected to the output of said thirdNAND gate and having a second input connected to the output of saidsecond NAND gate, and having its output connected to said first one ofsaid plurality of flip-flops; and

a second delay capacitor connected in circuit between said third NANDgate and said fifth NAND gate for delaying the propagation of a signalfrom said third NAND gate to said fifth NAND gate.

9. The apparatus of claim 1, wherein said first clock means includes:

means for generating a signal during the gauging cycle;

a first NAND gate connected to said means for generating a signal;

a second NAND gate connected to the output of said first NAND gate;

a third NAND gate connected to the output of said second NAND gate;

a delay capacitor connected in circuit between said second and thirdNAND gates for delaying the propagation of a signal from said second tosaid third NAND gate;

a fourth NAND gate connected to the output of said third NAND gate andto said means for generating a signal; and

a fifth NAND gate connected to the output of said fourth NAND gate,whereby the output of said fifth NAND gate is amachine clock pulse insynchronism with the index cycle of said inspection machine.

10. The apparatus of claim 1, wherein said second clock means includes asignal generator for generating a signal proportional to the speed ofsaid conveyor means.

1 l. The apparatus of claim 10, wherein said conveyor signal generatorcomprises, in combination:

a substantially U-shaped housing mounted adjacent said conveyor means;

an opaque code wheel having a plurality of openings extendingtherethrough, located at a common radial distance from the axis of saidcode wheel;

means for rotatably mounting said code wheel between the legs of saidhousing with its periphery in contact with said conveyor means, wherebysaid code wheel will rotate in proportion to the linear travel of saidconveyor means;

a light source positioned on the interior of one leg of said housingadjacent said disk at substantially the same radius as that of saidopenings; and

a photoelectric sensor positioned on the leg of said housing oppositesaid light source in alignment with said light source, whereby saidphotoelectric sensor will generate an output signal whenever one of theopenings in said code wheel rotates past said light source.

12. The apparatus of claim wherein said second clock means includes: asignal amplifier connected to said signal generator; a first NAND gateconnected to the output of said signal amplifier; a second NAND gateconnected to the output of said first NAND gate; a third NAND gateconnected to the output of said second NAND gate; a delay capacitorconnected in circuit between said second and third NAND gates fordelaying the propagation of a signal from said second NAND gate to saidthird NAND gate; a fourth NAND gate connected to the output of saidthird NAND gate and to the output of said. signal amplifier; and, afifth NAND gate connected to the output of said fourth NAND gate,whereby the output of said fifth NAND gate is a conveyor clock pulse insynchronism with the speed of travel of said conveyor means.

13. The apparatus of claim 1, wherein said first clock means includesmeans for generating a signal during the gauging cycle, and said secondmemory means comprises, in combination:

a plurality of flip-flops connected in series to form a shift register;

means connected to said plurality of flip-flops for setting an initialcondition in all of said flip-flops;

signal conditioning means having its output connected to the first oneof said plurality of flip-flops for resetting said flip-flop when asignal is presented by said first memory means and when said gaugingsignal is present;

means for connecting the output of said first memory means to a firstinput of said signal conditioning means; and

means for connecting said gauging signal to a second input of saidsignal conditioning means.

14. The apparatus of claim 13 wherein said signal conditioning meanscomprises, in combination:

a first NAND gate having its input connected to said first input of saidsignal conditioning means;

a second NAND gate having its input connected to said second input ofsaid signal conditioning means;

a third NAND gate having one input connected to the output of said firstNAND gate and having a second input connected to the output of saidsecond NAND gate, and having its output connected to said first one ofsaid plurality of flip-flops; and

a delay capacitor connected in circuit between said first NAND gate andsaid third NAND gate for delaying the propagation of a signal from saidfirst NAND gate to said third NAND gate.

15. A memory system for an article inspection machine which removesarticles one at a time from a continually moving article conveyor,serially indexes the,

articles through a plurality of inspectionstations, and returnsinspected articles to said conveyor, and wherein said inspection machineincludes article defect logic and detection means having a plurality ofoutput leads for generating a signal if an article is defective in oneor more aspects, comprising the combination of:

rejection means adjacent said conveyor downstream I of said inspectionmachine for removing defective articles from said conveyor;

first clock means for generating a series of machine clock pulses insynchronism with the indexcycle of said inspec tion machine;

first memory means connected to said article defect logic and detectionmeans and to said first clock means for storing defective articleinformation generated by said article defect logic and detection meansand for shifting said information in response to said machine clockpulses of said first clock means in synchronism with the index of saidarticle from inspection station to inspection station;

second clock means for generating a series of conveyor clock pulses insynchronism with the speed of travel of said conveyor, the frequency ofsaid machine clock pulses and said conveyor clock pulses beingindependent of one another; and

second memory means connected to said second clock means, said firstmemory means, and said reject means for receiving defective articleinformation from said first memory means as said article is returned tosaid conveyor, for shifting said information in response to saidconveyor clock pulses in synchronism with the movement of said articlealong said conveyor, and for actuating said rejection means as saidarticle reachessaid reject means to thereby reject a defective article.

16. The apparatus of claim 15, further including:

selector means connected to said article defect logic and detectionmeans for choosing one of said inspection stations to provide an outputfrom said selector meany when a defective article is present at saidinspection station; and

third memory means connected to said first clock means, said firstmemory means, said selector means, and said second memory means forreceiving defective article information from said selector means, forshifting said information in response to said machine clock pulses ofsaid first clock means in synchronism with the index of said defectivearticle from inspection station to inspection station, and for insertingsaid information in said second memory means in a position leading theposition wherein the same information is inserted in said second memorymeans by said first memory means.

17. The apparatus of claim 15, wherein said first memory meanscomprises, in combination:

a first plurality of flip-flops connected in series to form a shiftregister, said plurality of flip-flops being at least equal in number tothe number of inspection stations; e

a second plurality ofilip-flops connected in seriesto form a shiftregister, said second plurality of flipflops being at least equal innumber to the number of said first plurality of flip-flops;

means connected to said first and second plurality of flip-flops forsetting an initial condition in all of said first and second pluralityof flip-flops;

an article presence'switch adjacent said article inspection machine,connected to the first one of said second plurality of flip-flops, forovercoming the initial condition of said first one of said secondplurality of flip-flops when an article is present for inspection;

a first plurality of independent signal conditioning means, each of saidfirst plurality of signal conditioning means having one inputrespectively connected to one of said plurality of output leads fromsaid article defect logic and detection means, for resetting said firstplurality of flip-flops;

means for connecting the output of said first plurality of signalconditioning means respectively to an input of individual ones of saidfirst plurality of flipflops; and

means for connecting the outputs of said second plurality oi flip-flopsrespectively to a second input of each oi said first plurality of signalconditioning means, whereby said first plurality of signal conditioningmeans will reset said one of said first plurality of flip-flops onlywhen a defective article is detected and when said second plurality offlip-flops indicates the presence of an article at the inspectionstation where the defective article is detected.

18. The apparatus of claim 17, wherein said third memory meanscomprises, in combination:

a third plurality of flip-flops connected in series to 6 form a shiftregister, said third plurality of flip-flops being at least equal innumber to the number of inspection stations;

means connected to said third plurality of flip-flops for setting aninitial condition in all of said third plurality of flip-flops;

a second plurality of independent signal conditioning means, each ofsaid second plurality of signal conditioning means having one inputrespectively connected to one of the outputs of said selector means, forresetting said third plurality of flip-flops;

means for connecting the output of said second plurality of signalconditioning means respectively to an input of individual ones of saidthird plurality of flip-flops; and

means for connecting the outputs of said second plurality of flip-flopsrespectively to a second input of each of said second plurality ofsignal conditioning means, whereby said second plurality of signalconditioning means will reset said one of said third plurality offlip-flops only when a defective article is detected at the articleinspection station connected to one of said second plurality of signalconditioning means through said selector means and when said secondplurality of flip-flops indicates the presence of an article at theinspection station-where the defective article is detected. i

19. The" apparatus of claim 15, wherein' said first clock means includesmeans for generating a' signal during the gauging cycle, and said secondmemory means comprises, in combination:

a plurality of flip-flops connected in series to form a shiftregister; V

means connected to said plurality of flip-flops for setting an initialcondition in all of said flip-flops;

signal conditioning means having its output connected to the first oneof said plurality of flip-flops for resetting said flip-flop when asignal is presented by said first memory means and when said gaugingsignal is present;

means for connecting the output of said first memory means to a firstinput of said signal conditioning means; and

means for connecting said gauging signal to a second input of saidsignal conditioning means.

20. The apparatus of claim 16, wherein said first clock means includesmeans for generating a signal during the engaging cycle, and said secondmemory means comprises, in combination:

a plurality of flip-flops connected in series to form a shift register;

means connected to said plurality of flip-flops for setting an initialcondition in all of said flip-flops;

signal conditioning means having one output connected to the first oneof said plurality of flip-flops and a second output connected to asubsequent one of said flip-flops for resetting said first one and saidsubsequent one of said flip-flops when a signal is presented by saidfirst memory means and said third memory means and when said gaugingsignal is present or for resetting only said first one of saidflip-flops when a signal is presented only by said first memory meansand said gauging signal is present;

means for connecting the output of said third memory means to a firstinput of said signal conditioning means;

means for connecting said gauging signal to a second input of saidsignal conditioning means; and

1. Apparatus for inspecting and segregating articles comprising, incombination: conveyor means for moving said articles in single file; anarticle inspection machine located adjacent said conveyor means forreceiving said articles one at a time therefrom, serially indexing saidarticles through a plurality of inspection stations, and releasinginspected articles to said conveyor means; an article defect logic anddetection means connected to said plurality of inspection stations forgenerating one or more output signals if an article is defective in oneor more aspects, said article defect logic and detection means having aplurality of output leads at least equal in number to the number of saidinspection stations; a rejection means adjacent said conveyor means,downstream of said inspection machine, for removing defective articlesfrom said conveyor means; first clock means for generating a series ofmachine clock pulses in synchronism with the index cycle of saidinspection machine; first memory means connected to said article defectlogic and detection means and to said first clock means for storingdefective article information generated by said article defect logic anddetection means and for shifting said information in response to saidmachine clock pulses of said first clock means in synchronism with theindex of said article from inspection station to inspection station;second clock means for generating a series of conveyor clock pulses insynchronism with the speed of travel of said conveyor means, thefrequency of said machine clock pulses and said conveyor clock pulsesbeing independent of one another; and second memory means connected tosaid second clock means, said first memory means and said rejectionmeans for receiving defective article information from said first memorymeans as said article is released to said conveyor means, for shiftingsaid information in response to said conveyor clock pulses insynchronism with the movement of said article along said conveyor means,and for actuating said rejection means as said article reaches saidrejection means to thereby reject a defective article.
 2. The apparatusof claim 1, further including: selector means connected to said articledefect logic and detection means for choosing one of said inspectionstations to provide an output from selector means when a defectivearticle is present at said inspection station; and third memory meansconnected to said first clock means, said first memory means, saidselector means and said second memory means for receiving defectivearticle information from said selector means, for shifting saidinformation in response to said machine clock pulses of said first clockmeans in synchronism with the index of said defective article frominspection station to inspection station, and for inserting saidinformation in said second memory means in a position leading theposition wherein the same information is inserted in said second memorymeans by said first memory means.
 3. The apparatus of claim 2, whereinsaid first memory means comprises, in combination: a first plurality offlip-flops connected in series to form a shift register, said pluralityof flip-flops being at least equal in number to the number of inspectionstations; a second plurality of flip-flops connected in series to form ashift register, said second plurality of flip-flops being at least equalin number to the number of said first plurality of flip-flops; meansconnected to said first and second plurality of flip-flops for settingan initial condition in all of said first and second plurality offlip-floPs; an article presence switch adjacent said article inspectionmachine, connected to the first one of said second plurality offlip-flops, for overcoming the initial condition of said first one ofsaid second plurality of flip-flops when an article is present forinspection; a first plurality of independent signal conditioning means,each of said first plurality of signal conditioning means having oneinput respectively connected to one of said plurality of output leadsfrom said article defect logic and detection means, for resetting saidfirst plurality of flip-flops; means for connecting the output of saidfirst plurality of signal conditioning means respectively to an input ofindividual ones of said first plurality of flip-flops; and means forconnecting the outputs of said second plurality of flip-flopsrespectively to a second input of each of said first plurality of signalconditioning means, whereby said first plurality of signal conditioningmeans will reset said one of said first plurality of flip-flops onlywhen a defective article is detected and when said second plurality offlip-flops indicates the presence of an article at the inspectionstation where the defective article is detected.
 4. The apparatus ofclaim 3, wherein said third memory means comprises, in combination: athird plurality of flip-flops connected in series to form a shiftregister, said third plurality of flip-flops being at least equal innumber to the number of inspection stations; means connected to saidthird plurality of flip-flops for setting an initial condition in all ofsaid third plurality of flip-flops; a second plurality of independentsignal conditioning means, each of said second plurality of signalconditioning means having one input respectively connected to one of theoutputs of said selector means, for resetting said third plurality offlip-flops; means for connecting the output of said second plurality ofsignal conditioning means respectively to an input of individual ones ofsaid third plurality of flip-flops; and means for connecting the outputsof said second plurality of flip-flops respectively to a second input ofeach of said second plurality of signal conditioning means, whereby saidsecond plurality of signal conditioning means will reset said one ofsaid third plurality of flip-flops only when a defective article isdetected at the inspection station connected to one of said secondplurality of signal conditioning means through said selector means andwhen said second plurality of flip-flops indicates the presence of anarticle at the inspection station where the defective article isdetected.
 5. The apparatus of claim 3, wherein each of said firstplurality of signal conditioning means comprises, in combination: afirst NAND gate having its input side connected to one of said secondplurality of flip-flops; and a second NAND gate having one inputconnected to the output of said first NAND gate and having a secondinput connected to said article defect logic and detection means, andhaving its output connected to one of said first plurality offlip-flops.
 6. The apparatus of claim 4, wherein each of said secondplurality of signal conditioning means comprises, in combination: afirst NAND gate having its input side connected to one of said secondplurality of flip-flops; and a second NAND gate having one inputconnected to the output of said first NAND gate and having a secondinput connected to said selector means, and having its output connectedto one of said third plurality of flip-flops.
 7. The apparatus of claim2, wherein said first clock means includes means for generating a signalduring the gauging cycle, and said second memory means comprises, incombination: a plurality of flip-flops connected in series to form ashift register; means connected to said plurality of flip-flops forsetting an initial condition in all of said flip-flops; signalConditioning means having one output connected to the first one of saidplurality of flip-flops and a second output connectd to a subsequent oneof said flip-flops for resetting said first one and said subsequent oneof said flip-flops when a signal is presented by said first memory meansand said third memory means and when said gauging signal is present orfor resetting only said first one of said flip-flops when a signal ispresented only by said first memory means and said gauging signal ispresent; means for connecting the output of said third memory means to afirst input of said signal conditioning means; means for connecting saidgauging signal to a second input of said signal conditioning means; andmeans for connecting the output of said first memory means to a thirdinput of said signal conditioning means.
 8. The apparatus of claim 7wherein said signal conditioning means comprises, in combination: afirst NAND gate having its input connected to said first input of saidsignal conditioning means; a second NAND gate having its input connectedto said second input of said signal conditioning means; a third NANDgate having its input connected to said third input of said signalconditioning means; a fourth NAND gate having one input connected to theoutput of said first NAND gate and having a second input connected tothe output of said second NAND gate, and having its output connected tosaid subsequent one of said plurality of flip-flops; a first delaycapacitor connected in circuit between said first NAND gate and saidfourth NAND gate for delaying the propagation of a signal from saidfirst NAND gate to said fourth NAND gate; a fifth NAND gate having oneinput connected to the output of said third NAND gate and having asecond input connected to the output of said second NAND gate, andhaving its output connected to said first one of said plurality offlip-flops; and a second delay capacitor connected in circuit betweensaid third NAND gate and said fifth NAND gate for delaying thepropagation of a signal from said third NAND gate to said fifth NANDgate.
 9. The apparatus of claim 1, wherein said first clock meansincludes: means for generating a signal during the gauging cycle; afirst NAND gate connected to said means for generating a signal; asecond NAND gate connected to the output of said first NAND gate; athird NAND gate connected to the output of said second NAND gate; adelay capacitor connected in circuit between said second and third NANDgates for delaying the propagation of a signal from said second to saidthird NAND gate; a fourth NAND gate connected to the output of saidthird NAND gate and to said means for generating a signal; and a fifthNAND gate connected to the output of said fourth NAND gate, whereby theoutput of said fifth NAND gate is a machine clock pulse in synchronismwith the index cycle of said inspection machine.
 10. The apparatus ofclaim 1, wherein said second clock means includes a signal generator forgenerating a signal proportional to the speed of said conveyor means.11. The apparatus of claim 10, wherein said conveyor signal generatorcomprises, in combination: a substantially U-shaped housing mountedadjacent said conveyor means; an opaque code wheel having a plurality ofopenings extending therethrough, located at a common radial distancefrom the axis of said code wheel; means for rotatably mounting said codewheel between the legs of said housing with its periphery in contactwith said conveyor means, whereby said code wheel will rotate inproportion to the linear travel of said conveyor means; a light sourcepositioned on the interior of one leg of said housing adjacent said diskat substantially the same radius as that of said openings; and aphotoelectric sensor positioned on the leg of said housing opposite saidlight source in alignmenT with said light source, whereby saidphotoelectric sensor will generate an output signal whenever one of theopenings in said code wheel rotates past said light source.
 12. Theapparatus of claim 10 wherein said second clock means includes: a signalamplifier connected to said signal generator; a first NAND gateconnected to the output of said signal amplifier; a second NAND gateconnected to the output of said first NAND gate; a third NAND gateconnected to the output of said second NAND gate; a delay capacitorconnected in circuit between said second and third NAND gates fordelaying the propagation of a signal from said second NAND gate to saidthird NAND gate; a fourth NAND gate connected to the output of saidthird NAND gate and to the output of said signal amplifier; and, a fifthNAND gate connected to the output of said fourth NAND gate, whereby theoutput of said fifth NAND gate is a conveyor clock pulse in synchronismwith the speed of travel of said conveyor means.
 13. The apparatus ofclaim 1, wherein said first clock means includes means for generating asignal during the gauging cycle, and said second memory means comprises,in combination: a plurality of flip-flops connected in series to form ashift register; means connected to said plurality of flip-flops forsetting an initial condition in all of said flip-flops; signalconditioning means having its output connected to the first one of saidplurality of flip-flops for resetting said flip-flop when a signal ispresented by said first memory means and when said gauging signal ispresent; means for connecting the output of said first memory means to afirst input of said signal conditioning means; and means for connectingsaid gauging signal to a second input of said signal conditioning means.14. The apparatus of claim 13 wherein said signal conditioning meanscomprises, in combination: a first NAND gate having its input connectedto said first input of said signal conditioning means; a second NANDgate having its input connected to said second input of said signalconditioning means; a third NAND gate having one input connected to theoutput of said first NAND gate and having a second input connected tothe output of said second NAND gate, and having its output connected tosaid first one of said plurality of flip-flops; and a delay capacitorconnected in circuit between said first NAND gate and said third NANDgate for delaying the propagation of a signal from said first NAND gateto said third NAND gate.
 15. A memory system for an article inspectionmachine which removes articles one at a time from a continually movingarticle conveyor, serially indexes the articles through a plurality ofinspection stations, and returns inspected articles to said conveyor,and wherein said inspection machine includes article defect logic anddetection means having a plurality of output leads for generating asignal if an article is defective in one or more aspects, comprising thecombination of: rejection means adjacent said conveyor downstream ofsaid inspection machine for removing defective articles from saidconveyor; first clock means for generating a series of machine clockpulses in synchronism with the index cycle of said inspection machine;first memory means connected to said article defect logic and detectionmeans and to said first clock means for storing defective articleinformation generated by said article defect logic and detection meansand for shifting said information in response to said machine clockpulses of said first clock means in synchronism with the index of saidarticle from inspection station to inspection station; second clockmeans for generating a series of conveyor clock pulses in synchronismwith the speed of travel of said conveyor, the frequency of said machineclock pulses and said conveyor clock pulses being independent of oneanother; and second memorY means connected to said second clock means,said first memory means, and said reject means for receiving defectivearticle information from said first memory means as said article isreturned to said conveyor, for shifting said information in response tosaid conveyor clock pulses in synchronism with the movement of saidarticle along said conveyor, and for actuating said rejection means assaid article reaches said reject means to thereby reject a defectivearticle.
 16. The apparatus of claim 15, further including: selectormeans connected to said article defect logic and detection means forchoosing one of said inspection stations to provide an output from saidselector meany when a defective article is present at said inspectionstation; and third memory means connected to said first clock means,said first memory means, said selector means, and said second memorymeans for receiving defective article information from said selectormeans, for shifting said information in response to said machine clockpulses of said first clock means in synchronism with the index of saiddefective article from inspection station to inspection station, and forinserting said information in said second memory means in a positionleading the position wherein the same information is inserted in saidsecond memory means by said first memory means.
 17. The apparatus ofclaim 15, wherein said first memory means comprises, in combination: afirst plurality of flip-flops connected in series to form a shiftregister, said plurality of flip-flops being at least equal in number tothe number of inspection stations; a second plurality of flip-flopsconnected in series to form a shift register, said second plurality offlip-flops being at least equal in number to the number of said firstplurality of flip-flops; means connected to said first and secondplurality of flip-flops for setting an initial condition in all of saidfirst and second plurality of flip-flops; an article presence switchadjacent said article inspection machine, connected to the first one ofsaid second plurality of flip-flops, for overcoming the initialcondition of said first one of said second plurality of flip-flops whenan article is present for inspection; a first plurality of independentsignal conditioning means, each of said first plurality of signalconditioning means having one input respectively connected to one ofsaid plurality of output leads from said article defect logic anddetection means, for resetting said first plurality of flip-flops; meansfor connecting the output of said first plurality of signal conditioningmeans respectively to an input of individual ones of said firstplurality of flip-flops; and means for connecting the outputs of saidsecond plurality of flip-flops respectively to a second input of each ofsaid first plurality of signal conditioning means, whereby said firstplurality of signal conditioning means will reset said one of said firstplurality of flip-flops only when a defective article is detected andwhen said second plurality of flip-flops indicates the presence of anarticle at the inspection station where the defective article isdetected.
 18. The apparatus of claim 17, wherein said third memory meanscomprises, in combination: a third plurality of flip-flops connected inseries to form a shift register, said third plurality of flip-flopsbeing at least equal in number to the number of inspection stations;means connected to said third plurality of flip-flops for setting aninitial condition in all of said third plurality of flip-flops; a secondplurality of independent signal conditioning means, each of said secondplurality of signal conditioning means having one input respectivelyconnected to one of the outputs of said selector means, for resettingsaid third plurality of flip-flops; means for connecting the output ofsaid second plurality of signal conditioning means respectively to aninput of inDividual ones of said third plurality of flip-flops; andmeans for connecting the outputs of said second plurality of flip-flopsrespectively to a second input of each of said second plurality ofsignal conditioning means, whereby said second plurality of signalconditioning means will reset said one of said third plurality offlip-flops only when a defective article is detected at the articleinspection station connected to one of said second plurality of signalconditioning means through said selector means and when said secondplurality of flip-flops indicates the presence of an article at theinspection station where the defective article is detected.
 19. Theapparatus of claim 15, wherein said first clock means includes means forgenerating a signal during the gauging cycle, and said second memorymeans comprises, in combination: a plurality of flip-flops connected inseries to form a shift register; means connected to said plurality offlip-flops for setting an initial condition in all of said flip-flops;signal conditioning means having its output connected to the first oneof said plurality of flip-flops for resetting said flip-flop when asignal is presented by said first memory means and when said gaugingsignal is present; means for connecting the output of said first memorymeans to a first input of said signal conditioning means; and means forconnecting said gauging signal to a second input of said signalconditioning means.
 20. The apparatus of claim 16, wherein said firstclock means includes means for generating a signal during the engagingcycle, and said second memory means comprises, in combination: aplurality of flip-flops connected in series to form a shift register;means connected to said plurality of flip-flops for setting an initialcondition in all of said flip-flops; signal conditioning means havingone output connected to the first one of said plurality of flip-flopsand a second output connected to a subsequent one of said flip-flops forresetting said first one and said subsequent one of said flip-flops whena signal is presented by said first memory means and said third memorymeans and when said gauging signal is present or for resetting only saidfirst one of said flip-flops when a signal is presented only by saidfirst memory means and said gauging signal is present; means forconnecting the output of said third memory means to a first input ofsaid signal conditioning means; means for connecting said gauging signalto a second input of said signal conditioning means; and means forconnecting the output of said first memory means to a third input ofsaid signal conditioning means.
 21. A method for rejecting a defectivearticle downstream of an inspection machine which receives articles oneat a time from a conveyor, inspects said articles one at a time atmultiple inspection stations, indexes said articles from station tostation, generates a defect signal for a defective article, and returnsall articles one at a time to said conveyor, comprising the steps of:loading defective article information relating to a specific defectiveone of said articles into a first memory means; shifting saidinformation in said first memory means in synchronism with the index ofsaid defective article by said inspection machine; transferring saiddefective article information into a second memory means from said firstmemory means as said defective article is returned to said conveyor;shifting said defective article information in said second memory meansin synchronism with the movement of said defective article on saidconveyor downstream, away from said inspection machine; and rejectingsaid defective article from a stream of articles on said conveyor inresponse to the arrival of said defective article information at arejection means responsive to said defective article information.